At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Description:
- To complete advanced SoC block or fullchip level implementation from RTL to GDS, including hierarchical partition, floorplan, Synthesis, APR, Physical Verification, Power Integrity and timing Signoff/ECO.
- To well analysis and optimize timing and congestion with SDC/STA skill, advanced nodes knowledge, especial advanced CTS techniques
- To well analysis and optimize dynamic and leakage power with advanced low power methodology and real project experience
- To complete top level IO/bump/RDL routing and fullchip physical verification with advanced process nodes experience and Design Rule/IP/IO/STD application knowledge
- Use Tcl/Perl/Python to write scripts to improve work efficiency
Position Requirements:
- Master with 3+ years working experience or Bachelor with 6+ years’ experience in IC design.
- Ability to understand and articulate technical issues, (and knowledge of) design products and their applications.
- Requires working knowledge of one or more programming languages, and effective communication and soft skills.
- Be familiar with Genus/Innovus/Voltus/Tempus product is a plus.
- Good knowledge of verilog/spice/sdc/upf/lef/def/spef.
- Good communication in English and good work attitude.
- Be familiar with shell/Perl/Tcl etc. script language.
We’re doing work that matters. Help us solve what others can’t.
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